Dual poly deposition and through gate oxide implants

ABSTRACT

Dopants are implanted at relatively high energies into an unmasked first region of a semiconductor substrate through a thin layer of gate electrode material and a gate dielectric layer. Lower energy dopants are then implanted into the thin layer of gate electrode material. The first region is then masked off, and the process is repeated in a previously masked, but now unmasked, second region of the semiconductor substrate. A second (and usually thicker) layer of gate electrode material is then formed over the thin layer of gate electrode material. The layer of thick gate electrode material, the layer of thin gate electrode material and the layer of gate dielectric material are patterned to form one or more gate structures over the doped regions of the substrate. Source and drain regions are formed in the substrate regions adjacent to the gate structures to establish one or more MOS transistors.

FIELD OF INVENTION

The present invention relates generally to semiconductor processing, andmore particularly to performing a dual poly deposition, implantingdopants through a gate oxide, and dual pre-pattern poly doping.

BACKGROUND OF THE INVENTION

It can be appreciated that semiconductor processing can comprisehundreds of steps, during which many copies of an integrated circuit canbe formed on a single semiconductor substrate or workpiece, generallyknown as a wafer. Generally, such processes involve creating severallayers on and in the substrate that ultimately form a completeintegrated circuit. This layering process can create electrically activeregions in and on the semiconductor wafer surface. In ametal-oxide-semiconductor (MOS) transistor, for example, a gatestructure is created, which can be energized to establish an electricfield within a semiconductor channel, by which current is enabled toflow between a source region and a drain region within the transistor.The source and drain regions facilitate this conductance by virtue ofcontaining a majority of hole (p type) or electron (n type) carriers.

It can also be appreciated that there is an ongoing desire to streamlinefabrication processes to reduce fabrication times and cut costs.Likewise, it is desirable to enhance transistor operation. Accordingly,techniques that allow MOS transistors to be fabricated in a costeffective manner, while also improving the functionality of resultingtransistors are desirable.

SUMMARY OF THE INVENTION

The following presents a simplified summary of the invention in order toprovide a basic understanding of some aspects of the invention. Thissummary is not an extensive overview of the invention. It is intendedneither to identify key or critical elements of the invention nor todelineate the scope of the invention. Rather, its primary purpose ismerely to present one or more concepts of the invention in a simplifiedform as a prelude to the more detailed description that is presentedlater.

Implantations of one or more types of dopants to form one or more MOStransistors are performed through a thin layer of gate electrodematerial and a layer of gate dielectric material. Additionally, dopantsare implanted into the thin layer of gate electrode material, where atleast some of this layer serves as a lower portion of a gate electrodeof a transistor. Locating the dopants in this part of the gate electrodeenhances the operation of the transistor by mitigating the likelihood ofpoly depletion, for example. These two implantations are performed usingthe same mask which reduces the number of masking steps needed andthereby streamlines the fabrication process.

To the accomplishment of the foregoing and related ends, the followingdescription and annexed drawings set forth in detail certainillustrative aspects and implementations of the invention. These areindicative of but a few of the various ways in which one or more aspectsof the present invention may be employed. Other aspects, advantages andnovel features of the invention will become apparent from the followingdetailed description of the invention when considered in conjunctionwith the annexed drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flow diagram illustrating an exemplary methodology forforming one or more MOS transistors.

FIGS. 2-11 are cross-sectional views of a semiconductor substratewherein one or more exemplary MOS transistors are formed.

DETAILED DESCRIPTION OF THE INVENTION

An exemplary methodology 100 for forming one or more MOS transistors isillustrated in FIG. 1, and FIGS. 2-11 are cross sectional views of asemiconductor substrate 200 wherein such a method is implemented. Whilethe method 100 is illustrated and described below as a series of acts orevents, it will be appreciated that the present invention is not limitedby the illustrated ordering of such acts or events. For example, someacts may occur in different orders and/or concurrently with other actsor events apart from those illustrated and/or described herein. Inaddition, not all illustrated acts may be required to implement amethodology disclosed herein. Further, one or more of the acts depictedherein may be carried out in one or more separate acts and/or phases.

The methodology 100 begins at 102 wherein a layer of gate dielectricmaterial 202 is formed over a semiconductor substrate 200 (FIG. 2).Although not illustrated, it will be appreciated that isolation regions(e.g., STI) can be formed in the substrate 200 prior to forming thelayer of gate dielectric material 202. Such isolation regions are formedat select locations in the substrate 200, and serve to separatestructures from one another, such as resulting transistors, for example.It will be appreciated that substrate as referred to herein may compriseany type of semiconductor body (e.g., silicon, SiGe, SOI) such as asemiconductor wafer or one or more die on a wafer, as well as any othertype of semiconductor and/or epitaxial layers grown thereon and/orotherwise associated therewith. The layer of gate dielectric material202 can be formed to a thickness of about 1 nanometer or more, and canhave an equivalent oxide thickness (EOT) of between about 3 nanometersand about 0.5 nanometers, for example. The layer of gate dielectricmaterial 202 can comprise a high-k dielectric material, for example. Adielectric material having a k of about 7.8 and a thickness of about 10nm, for example, is substantially electrically equivalent to an oxidegate dielectric having a k of about 3.9 and a thickness of about 5 nm.The layer of gate dielectric material 202 may include, for example, anyone or more of the following, either alone or in combination: aluminumoxide (Al₂O₃), zirconium silicate, hafnium silicate, hafnium siliconoxynitride, hafnium oxynitride, zirconium oxynitride, zirconium siliconoxynitride, hafnium silicon nitride, lanthanum oxide (La₂O₃), hafniumoxide (HfO₂), zirconium oxide (ZrO₂), cerium oxide (CeO₂), bismuthsilicon oxide (Bi₄Si₂O₁₂), titanium dioxide (TiO₂), tantalum oxide(Ta₂O₅), tungsten oxide (WO₃), yttrium oxide (Y₂O₃), lanthanum aluminumoxide (LaAlO₃), barium strontium titanate, barium strontium oxide,barium titanate, strontium titanate, PbZrO₃, PST, PZN, PZT and PMN.

A first layer of gate electrode material 204 is then formed over thelayer of gate dielectric material 202 at 104 (FIG. 3). This layer ofgate electrode material 204 may be formed to a thickness of betweenabout 80 Angstroms and about 300 Angstroms, for example. The first layerof gate electrode material 204 generally includes polysilicon, SiGe orother semiconductor materials. It will be appreciated that the layer ofgate dielectric material 202 and the first layer of gate electrodematerial 204 can be applied to the substrate 200 in any number of ways,such as with spin-on techniques, sputtering techniques (e.g., magnetronor ion beam sputtering), growth and/or deposition techniques such aschemical vapor deposition (CVD), for example.

At 106 part of the substrate is masked off so that one or more dopantscan be selectively implanted into a first unmasked area of thesubstrate. For example, a first resist 206 can be formed over the entiresubstrate 200 and patterned in accordance with lithographic techniquesso that an exposed portion 210 of the substrate 200, wherein a firsttype of transistor is to be formed, can be doped to form a first welltherein (FIG. 4). The first resist 206 is formed to a thicknesssufficient to block subsequently implanted dopants. For example, thefirst resist can be formed to a thickness of between about 500nanometers and about 1500 nanometers. It will be appreciated thatlithography can be implemented to effect much of the patterning andprocessing described herein, where lithography broadly refers toprocesses for transferring one or more patterns between various media.In lithography, a light sensitive resist coating is formed over one ormore layers to which a pattern is to be transferred. The resist coatingis then patterned by exposing it to one or more types of radiation orlight which (selectively) passes through an intervening lithography maskcontaining the pattern. The light causes exposed or unexposed portionsof the resist coating to become more or less soluble, depending on thetype of resist used. A developer is then used to remove the more solubleareas leaving the patterned resist. The patterned resist can then serveas a mask for the underlying layer or layers which can be selectivelytreated (e.g., doped).

Accordingly, at 108 a first implantation 216 is performed to implantdopants into the first unmasked region 210 of the substrate 200 (FIG.5). It will be appreciated that this implantation 216 may actuallycomprise one or more implantations performed at one or more doses and/orenergies with one or more different species. The implanted dopants havea first electrical conductivity type so that the first well 212possesses the first electrical conductivity type. By way of example, thedopants may be p type dopants so that the first well 212 has a p typeelectrical conductivity. As such, one or more NMOS transistors can beformed in the first region 210. The implantation 216 is performed insuch a manner that the dopants pass through the first layer of gateelectrode material 204 and the layer of gate dielectric material 202.For example, Boron can be implanted at a dose of between about 1e12/cm²and about 3e13/cm² and an energy of between about 20 KeV and about 300KeV.

At 110, a second implantation 220 is performed to implant dopants havingthe first electrical conductivity type into a first region 222 of thefirst layer of gate electrode material 204 overlying the first region210 of the substrate 200, where these dopants generally do not penetrateinto and/or are stopped by the layer of gate dielectric material 202(FIG. 6). By way of example, Arsenic can be implanted at a dose ofbetween about 1e15/cm² and about 4e15/cm² and an energy of between about500 eV and about 2.5 KeV. Additionally, this implantation may compriseone or more implantations performed at one or more doses and/or energieswith one or more different species. At 112, the first patterned resist206 is stripped and a second resist 226 is formed and patterned so thata second region 230 of the substrate 200 is unmasked and a second well232 can be formed therein (FIG. 7). Similar to resist 206, the secondresist 226 is formed to a thickness (e.g., between about 500 nanometersand about 1500 nanometers) sufficient to block subsequently implanteddopants.

A third implantation 236 is thus performed at 114 to establish thesecond well 232 in the second region 230 of the substrate 200 (FIG. 8).The implanted dopants have a second electrical conductivity type so thatthe second well 232 possesses the second electrical conductivity type.By way of example, the dopants may be n type dopants so that the secondwell 232 has an n type electrical conductivity. As such, one or morePMOS transistors can be formed in the second region 230. Likeimplantation 216, implantation 236 is performed so that the dopants passthrough the first layer of gate electrode material 204 and the layer ofgate dielectric material 202. For example, Phosphorus can be implantedat a dose of between about 1e12/cm² and about 3e13/cm² and an energy ofbetween about 60 KeV and about 500 KeV. Similarly, this implantation 236may comprise one or more implantations performed at one or more dosesand/or energies with one or more different species.

At 116, a fourth implantation 240 is performed to implant dopants havingthe second electrical conductivity type into a second region 242 of thefirst layer of gate electrode material 204 overlying the second region230 of the substrate 200, where these dopants generally do not penetrateinto and/or are stopped by the layer of gate dielectric material 202(FIG. 9). By way of example, BF2 can be implanted at a dose of betweenabout 1e15/cm² and about 4e15/cm² and an energy of between about 500 eVand about 4 KeV. Additionally, this implantation may comprise one ormore implantations performed at one or more doses and/or energies withone or more different species.

The second patterned resist 226 is then stripped and a second layer ofgate electrode material 250 is formed over the first layer of gateelectrode material 204 at 118 (FIG. 10). The second layer of gateelectrode material 250 may be formed to a thickness of between about 800Angstroms and about 1000 Angstroms, for example. Like the first layer ofgate electrode material 204, the second layer of gate electrode material250 generally includes polysilicon, SiGe or other semiconductormaterials. The second layer of gate electrode material 250 is generallyformed by a blanket deposition process wherein masking is notimplemented.

The second layer of gate electrode material 250, the first layer of gateelectrode material 204 and the layer of gate dielectric material 202 arethen patterned at 120 to form one or more gate structures 252, 254 overthe first 210 and second 230 regions, respectively, of the substrate 200(FIG. 11). The bottom portions 222, 242 of the gate structures 252, 254thus have a dopant concentration of between about 1e21/cm² and about4e21/cm². With the patterned gate structures 252, 254 formed, LDD, orother source drain extension implants (not shown) can be performed, forexample, depending upon the type(s) of transistors to be formed, and oneor more left and right offset and/or sidewall spacers (not shown) can beformed along left and right lateral sidewalls of the patterned gatestructures 252, 254.

Implants to form respective source 262, 264 and drain 266, 268 regionsare then performed, wherein any suitable masks and implantationprocesses may be used in forming the source and drain regions to achievedesired transistor types (FIG. 11). It will be appreciated thatrespective channel regions 270, 272 are thus defined between the sourceand drain regions 262, 266 and 264, 268 of the different transistors282, 284. It will also be appreciated that sidewall spacers generallyserve to guide dopants into select locations in the substrate 200, suchas in forming the source 262, 264 and drain 266, 268 regions, forexample.

The transistors 282, 284, and more particularly the first 210 and second230 regions of the substrate 200 and the first 212 and second 232 wellscontained therein, are electrically separated from one another by one ormore (previously formed) isolation (e.g., dielectric) regions 290 formedin the substrate 200. In the illustrated example, a single transistor282 is formed over the first region 210 and a single transistor 284 isformed over the second region 230. It will be appreciated, however, thatany number of transistors (including none/zero transistors) can beformed in either of the different regions 210, 230. Once thesource/drain regions are formed, the methodology 100 advances to 122,and ends thereafter, wherein further back end processing can beperformed at 122, such as the formation and/or patterning of one or moreadditional conductive and/or non-conductive layers.

It can be appreciated that the gate structures 252, 254 thus compriserespective gate electrodes 222, 250 and 242, 250 and gate dielectrics202. It will be appreciated that the gate electrodes yield a contactarea or surface that provides a means for applying a voltage to thetransistors 282, 284 or otherwise biasing the transistors 282, 284. Thegate dielectrics generally serve to prevent large ‘leakage’ currentsfrom flowing from the conductive gate electrodes into the conductivechannel regions 270, 272 when voltages are applied to electrodes, whilealso allowing applied gate voltages to set up electric fields within thechannel regions 270, 272 in a controllable manner.

It will be appreciated that the operation of the transistors 282, 284,and in particular current flowing therein, is also a function of thedoping of the gate electrodes. In some instances the gate electrodes runout of or become depleted of dopants or electrical carriers. If thishappens, the transistors do not function as desired. This depletion isoften a function of the location of the dopants within the electrodes,and more particularly because the dopants are located too far away fromthe channel regions. Accordingly, because dopants are implanted (e.g.,at 110/220 and 116/240) in the thin layer of gate electrode material204, and thus closer to the channel regions 270, 272, transistorsfashioned as described herein function in a more desirable manner thantransistors that do not have a high concentration of dopants in a bottomportion (e.g., 222, 242) of their gate electrodes (at least relative tothe upper portions of their gate electrodes). In particular, transistorsfashioned as described herein are less likely to experience gateelectrode (e.g., polysilicon) depletion.

Additionally, forming transistors as described herein streamlines thefabrication process, at least, by reducing the number of masks that areneeded. In particular, since dopants are implanted through the gatedielectric 202 and first gate electrode 204 at 108/216 and 114/236 toform the first 212 and second 232 wells, merely two masks 206, 226 areneeded. However, more masks (e.g., four) are needed if the wells are notformed by implanting through the gate dielectric 202 and the first gateelectrode 204 layer. For example, first and second masks would be neededto establish the first 212 and second 232 wells. Additionally, third andfourth masks would also be needed to then dope the single layer of gateelectrode material (e.g., where one thick layer of gate electrodematerial is utilized as opposed to a thin layer 204 and a thicker layer250 as described herein). Further, since the dopants are applieddirectly to the bottom portions 222, 242 of the transistors 282, 284, anannealing or other heat treatment process is not needed to force thedopants down toward the bottom of the single thick gate electrode layer,thus substantially lessening a required thermal budget. Also, implantingdirectly into the lower portion of the gate electrode provides a muchgreater degree of control over where the dopants ultimately end up inthe gate electrode, particularly as compared to heating the dopants tomove them around.

Implanting dopants through the (thin) layer of gate electrode material204 to form the first 212 and second 232 wells also allows a much lowerenergy to be used to implant the dopants, as compared to having toimplant the dopants thorough a single thicker layer of gate electrodematerial. Using lower energy implants is more desirable as it is lessdestructive (e.g., to the gate dielectric layer). Implanting through thethinner layer of gate electrode material 204 also allows more controlover the implantation process, such as to achieve a retrograde profile,for example, where a retrograde profile refers to a concentration ofdopants that increases in relation to implantation depth (e.g., dopantconcentration increases as depth increases). It will be appreciated thatachieving a retrograde profile is desirable since such a dopantdistribution allows for desired device performance.

In one example, a retrograde profile in a transistor fashioned asdescribed herein comprises a dopant of Arsenic at a concentration ofbetween about 1e18/cm³ and about 2e18/cm³ at a depth of between about200 Angstroms and about 400 Angstroms and having a concentration that isreduced to between about 1e18/cm³ and about 3e17/cm³ as the implantationdepth is reduced to between about 0 Angstroms and about 100 Angstroms.Stated another way, a higher dopant concentration is produced deeper inthe substrate, while a lighter dopant concentration is produced atshallower locations in the substrate. The deeper dopant concentration isthus between about 1e18/cm³ and about 2e18/cm³ at a depth of betweenabout 200 Angstroms and about 400 Angstroms, whereas the dopantconcentration is merely between about 1e18/cm³ and about 3e17/cm³ at adepth of between about 0 Angstroms and about 100 Angstroms. It can beappreciated that a retrograde profile is difficult to achieve whenimplanting through a thick layer of gate electrode material since thedopants are slowed down by the thickness of the layer.

Implanting through the (thin) layer of gate electrode material 204 alsoallows more uniform implantations to be achieved (e.g., a consistentretrograde profile across the substrate). Implanting through a thicklayer of gate electrode material can result in non-uniform implantationsas the trajectory of the dopants can be interfered with by the by thethick layer. Additionally, a thicker layer of gate electrode material ismore likely to embody non-uniformities and/or undulations than the thinlayer of gate electrode material 204 which can be formed more precisely.And, such imperfections may be reflected in or transferred to theimplanted dopants. For example, dips in a thick layer of gate electrodematerial may allow dopants to be implanted more deeply, while elevatedportions of a thick layer of gate electrode material may cause dopantsto be implanted less deeply.

It will be appreciated that while reference is made throughout thisdocument to exemplary structures in discussing aspects of methodologiesdescribed herein (e.g., those structures presented in FIGS. 2-11 whilediscussing the methodology set forth in FIG. 1), that thosemethodologies are not to be limited by the corresponding structurespresented. Rather, the methodologies (and structures) are to beconsidered independent of one another and able to stand alone and bepracticed without regard to any of the particular aspects depicted inthe Figs.

Although the invention has been shown and described with respect to oneor more implementations, equivalent alterations and modifications willoccur to others skilled in the art based upon a reading andunderstanding of this specification and the annexed drawings. Theinvention includes all such modifications and alterations and is limitedonly by the scope of the following claims. In addition, while aparticular feature or aspect of the invention may have been disclosedwith respect to only one of several implementations, such feature oraspect may be combined with one or more other features or aspects of theother implementations as may be desired and advantageous for any givenor particular application. Furthermore, to the extent that the terms“includes”, “having”, “has”, “with”, or variants thereof are used ineither the detailed description or the claims, such terms are intendedto be inclusive in a manner similar to the term “comprising.” Also, theterm “exemplary” is merely meant to mean an example, rather than thebest. It is also to be appreciated that features and/or elementsdepicted herein are illustrated with particular dimensions relative toone another (e.g., layer to layer dimensions, orientations and/orscaling) for purposes of simplicity and ease of understanding, and thatactual dimensions of the elements may differ substantially from thatillustrated herein.

1. A MOS transistor comprising: a gate structure, comprising: a gatedielectric formed over a semiconductor substrate; a first gate electrodeformed over the gate dielectric; and a second gate electrode formed overthe first gate electrode; a source region formed in the semiconductorsubstrate adjacent to one side of the gate structure; and a drain regionformed in the semiconductor substrate adjacent to the other side of thegate structure.
 2. The transistor of claim 1, where the first gateelectrode comprises a dopant of Arsenic at a concentration of betweenabout 1e15/cm² and about 4e15/cm².
 3. The transistor of claim 2, wherethe first gate electrode is formed to a thickness of between about 80Angstroms and about 300 Angstroms and the second gate electrode isformed to a thickness of between about 800 Angstroms and about 1000Angstroms.
 4. The transistor of claim 3, where the source and drainregions are formed in a well region in the semiconductor substrate,where the well region has a retrograde profile of a dopant of Boron at aconcentration of between about 1e18/cm³ and about 2e18/cm³ at a depth ofbetween about 200 Angstroms and about 400 Angstroms and a concentrationof between about 3e17/cm³ and about 1e18/cm³ at a depth of between about0 Angstroms and about 100 Angstroms.